Bi-Junction Transistors (PHC504)

Transistors

Introduction

The transistor is a three-layer semiconductor device consisting of either two n - and one p -type layers of material or two p - and one n -type layers of material. The former is called an npn transistor , and the latter is called a pnp transistor .
Transistors
Fig
Transistors
Fig
Transistors
Fig
IE=IC+IB I_{E}=I_{C}+I_{B} IC=ICmajority+IBminority I_{C}=I_{C_{majority}}+I_{B_{minority}}

Common-Base Configuration

Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
IC=IE I_{C}=I_{E} VBE=0.7 V V_{BE}=0.7 ~ V In the dc mode the levels of I C and I E due to the majority carriers are related by a quantity called alpha and defined by the following equation: αdc=ICIE \alpha_{dc}=\frac{I_{C}}{I_{E}} IC=αIE+ICBO I_{C}=\alpha I_{E} + I_{CBO} AC Mode αac=ΔICΔIE \alpha_{ac}=\frac{\Delta I_{C}}{\Delta I_{E}}

Common-Emitter Configuration

Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
IC=αIE+ICBO I_{C}=\alpha I_{E}+I_{CBO} IC=α(IC+IB)+ICBO I_{C}=\alpha (I_{C}+I_{B})+I_{CBO} (1α)IC=αIB+ICBO (1-\alpha)I_{C}=\alpha I_{B} +I_{CBO} IC=αIB(1α)+ICBO(1α) I_{C}=\frac{\alpha I_{B}}{(1-\alpha)} +\frac{I_{CBO}}{(1-\alpha)} the collector current defined by the condition IB=0 μAI_{B} = 0~\mu A will be assigned the notation indicated by the following equation: ICEO=ICBO(1α) I_{CEO}=\frac{I_{CBO}}{(1-\alpha)} For linear (least distortion) amplification purposes, cutoff for the common-emitter configuration will be defined by IC=ICEOI_{C}=I_{CEO}.

Beta β\beta

In the dc mode the levels of I C and I B are related by a quantity called beta and defined by the following equation: βdc=ICIB \beta_{dc}=\frac{I_{C}}{I_{B}} For ac situations an ac beta is defined as follows: βac=ΔICΔIB \beta_{ac}=\frac{\Delta I_{C}}{\Delta I_{B}} IE=IC+IB I_{E}= I_{C}+I_{B} ICα=IC+ICβ \frac{I_{C}}{\alpha}= I_{C}+\frac{I_{C}}{\beta} or 1α=1+1β \frac{1}{\alpha}= 1+\frac{1}{\beta} or α=ββ+1 \alpha = \frac{\beta}{\beta +1} or β=α1α \beta = \frac{\alpha}{1-\alpha} Additionally, ICEO=ICBO(1α) I_{CEO}=\frac{I_{CBO}}{(1-\alpha)} but, 11α=β+1 \frac{1}{1-\alpha} = \beta + 1 or ICEO=(β+1) ICBO I_{CEO}=(\beta + 1)~I_{CBO} or ICEO=βICBO I_{CEO}=\beta I_{CBO} and IC=βIB I_{C}=\beta I_{B} also, IE=IC+IB=βIB+IB I_{E}=I_{C}+I_{B} = \beta I_{B}+I_{B} or IE=(β+1)IB I_{E}=(\beta + 1)I_{B}

Common-Collector Configuration

Transistors
Fig

Limits of Operation

For each transistor there is a region of operation on the characteristics that will ensure that the maximum ratings are not being exceeded and the output signal exhibits minimum distortion.
Transistors
Fig
The maximum dissipation level is defined by the following equation: PCmax=VCEIC P_{C_{max}}=V_{CE}I_{C} The cutoff region is defined as that region below IC = ICEO. This region must also be avoided if the output signal is to have minimum distortion. The transistors are generally operated as per the condition given below: ICEOICICmax I_{CEO}\leq I_{C} I_{C_{max}} VCEsatVCEVCEmax V_{CE_{sat}}\leq V_{CE} V_{CE_{max}} VCEICPCmax V_{CE}I_{C} \leq P_{C_{max}} For the common-base characteristics the maximum power curve is defined by the following product of output quantities: PCmax=VCBIC P_{C_{max}}=V_{CB}I_{C}

Operating point

1. The base–emitter junction must be forward-biased (p-region voltage more positive), with a resulting forward-bias voltage of about 0.6 V to 0.7 V. 2. The base–collector junction must be reverse-biased (n-region more positive), with the reverse-bias voltage being any value within the maximum limits of the device. Operation in the cutoff, saturation, and linear regions of the BJT characteristic are provided as follows: 1. Linear-region operation: Base–emitter junction forward-biased Base–collector junction reverse-biased 2. Cutoff-region operation: Base–emitter junction reverse-biased Base–collector junction reverse-biased 3. Saturation-region operation: Base–emitter junction forward-biased Base–collector junction forward-biased
Transistors
Fig

Fixed-Bias Configuration

Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig

Emitter-Bias Configuration

Transistors
Fig
Transistors
Fig
Transistors
Fig

Voltage Divider bised Configuration

Transistors
Fig
Transistors
Fig

Exact Analysis

The Thévenin equivalent network for the network to the left of the base terminal can then be found in the following manner:

Thévenin Resistance RThR_{Th} The voltage source is replaced by a short-circuit equivalent as

RTh=R1R2R_{Th} = R_{1} || R_{2} Thévenin voltage EThE_{Th} The voltage source VCCV_{CC} is returned to the network and the open-circuit Thévenin voltage determined as follows:

Applying the voltage-divider rule gives ETh=VR2=R2VCC(R1+R2) E_{Th} = V_{R_{2}} = \frac{R_{2}V_{CC}}{(R_{1} + R_{2})}

The Thévenin network is then redrawn and IBQI_{BQ} can be determined by first applying Kirchhoff's voltage law in the clockwise direction for the loop indicated:

EThIBRThVBEIERE=0E_{Th} - I_{B}R_{Th} - V_{BE} - I_{E}R_{E} = 0

Substituting IE=(β+1)IBI_{E} = (\beta + 1)I_{B} and solving for IBI B yields

IB=(EThVBE)(RTh+(β+1)RE)I_{B} = \frac{(E_{Th} - V_{BE})}{(R_{Th} + (\beta + 1)R_{E})}

Although initially appears to be different from those developed earlier, note that the numerator is again a difference of two voltage levels and the denominator is the base resistance plus the emitter resistor reflected by (β+1)(\beta + 1).

Once IBI_{B} is known, the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration. That is,

VCE=VCCIC(RC+RE) V_{CE} = V_{CC} - I_{C}(R_{C} + R_{E})

The remaining equations for VEV_{E}, VCV_{C}, and VBV_{ B} are also the same as those obtained for the emitter-bias configuration.

Transistors
Fig

Approximate Analysis

The input section of the voltage-divider configuration can be represented by the network. The resistance RiR_{i} is the equivalent resistance between base and ground for the transistor with an emitter resistor RER_{E}.

Transistors
Fig

The emitter resistor, which is part of the collector–emitter loop, “appears as” (β+1)RE(\beta + 1)R_{E} in the base–emitter loop.

Ri=(β+1)RER_{i}= (\beta + 1)R_{E}

If RiR_{i} is much larger than the resistance R2R_{2} , the current IBI_{B} will be much smaller than I2I_{2} (current always seeks the path of least resistance) and I2I_{2} will be approximately equal to I1I_{1}. If we accept the approximation that IBI_{B} is essentially 00 AA compared to I1I_{1} or I2I_{2} , then I1=I2I_{1} = I_{2}, and R1R_{1} and R2R_{2} can be considered series elements. The voltage across R2R_{2} , which is actually the base voltage, can be determined using the voltage-divider rule. That is,

VB=R2VCC(R1+R2)V_{B} = \frac{R_{2}V_{CC}}{(R_{1} + R_{2})}

Because Ri=(β+1)REβRER_{i} = (\beta + 1)R_{E} \cong \beta R_{E} the condition that will define whether the approximate approach can be applied is

βRE10R2\beta R_{E} \geq 10R_{2} In other words, if β\beta times the value of RER_{E} is at least 10 times the value of R2R_{2}, the approximate approach can be applied with a high degree of accuracy.

Once VBV_{B} is determined, the level of VEV_{E} can be calculated from

VE=VBVBEV_{E} = V_{B} - V_{BE} and the emitter current can be determined from IE=VEREI_{E} = \frac{V_{E}}{R_{E}}

and ICQIEI_{CQ} \cong I_{E}

The collector-to-emitter voltage is determined by VCE=VCCICRCIEREV_{CE} = V_{CC} - I_{C}R_{C} - I_{E}R_{E}

but because IEICIE \cong IC,

VCEQ=VCCIC(RC+RE)V_{CEQ} = V_{CC} - I_{C}(R_{C} + R_{E})

In the sequence of calculations β\beta does not appear and IBI_{B} was not calculated. The QQ-point (as determined by ICQI_{CQ} and VCEQV_{CEQ}) is therefore independent of the value of betabeta.

Emitter Follower Configuration

Emitter follower configuration is where the output is taken off the emitter terminal as shown in figure. The configuration is not the only one where the output can be taken off the emitter terminal. In fact, any of the configurations just described can be used so long as there is a resistor in the emitter leg.

Transistors
Fig

Applying Kirchhoff's voltage rule to the input circuit will result in

IBRBVBEIERE+VEE=0-I_{B}R_{B} - V_{BE} - I_{E}R_{E} + V_{EE} = 0

and using IE=(β+1)IBI_{E} = (\beta + 1)I_{B}

IBRB+(β+1)IBRE=VEEVBEI_{B}R_{B} + (\beta + 1)I_{B}R_{E} = V_{EE} - V_{BE}

so that

IB=VEEVBERB+(β+1)REI_{B} = \frac{V_{EE} - V_{BE}}{R_{B} + (\beta + 1)R_{E}}

For the output network, an application of Kirchhoff's voltage law will result in

VCEIERE+VEE=0-V_{CE} - I_{E}R_{E} + V_{EE} = 0

and

VCE=VEEIEREV_{CE} = V_{EE} - I_{E}R_{E}

R-C Coupled BJT amplifier

The collector output of one stage is fed directly into the base of the next stage using a coupling capacitor CCC_{C}. The capacitor is chosen to ensure that it will block dc between the stages and act like a short circuit to any ac signal. The network has two voltage-divider stages, but the same RCRC coupling can be used between any combination of networks such as the fixed-bias or emitter-follower configurations. Substituting an open-circuit equivalent for CCC_{C} and the other capacitors of the network will result in the two bias arrangements. The methods of analysis introduced in this chapter can then be applied to each stage separately since one stage will not affect the other.

Transistors
Fig

Darlington Pair

The Darlington configuration feeds the output of one stage directly into the input of the succeeding stage. Since the output is taken directly off the emitter terminal, you will find in the next chapter that the ac gain is very close to 1 but the input impedance is very high, making it attractive for use in amplifiers operating off sources that have a relatively high internal resistance. If a load resistor were added to the collector leg and the output taken off the collector terminal, the configuration would provide a very high gain.

Transistors
Fig

Transistor Switching Network

The application of transistors is not limited solely to the amplification of signals. Through proper design, transistors can be used as switches for computer and control applications. The network can be employed as an inverter in computer logic circuitry. Note that the output voltage VCV_{C} is opposite to that applied to the base or input terminal. In addition, note the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector or output side, and for computer applications is typically equal to the magnitude of the “high” side of the applied signal—in this case 5 V. The resistor RBR_{B} will ensure that the full applied voltage of 55 VV will not appear across the base-to-emitter junction. It will also set the IBI_{ B} level for the “on” condition. Proper design for the inversion process requires that the operating point switch from cutoff to saturation along the load line.

Transistors
Fig
Transistors
Fig

In Fig this requires that IB50I_{B} \cong 50 mAmA. The saturation level for the collector current for the circuit of Fig. is defined by

ICsat=VCCRCI_{C_{sat}} = {V_{CC}}{R_{C}}

The level of IBI_{B} in the active region just before saturation results can be approximated by the following equation:

IBmaxICsatbdcI_{B_{max}} \cong {I_{C_{sat}}} {b_{dc}}

For the saturation level we must therefore ensure that the following condition is satisfied:

IB>ICsatbdcI_{B} \gt \frac{I_{C_{sat}}}{b_{dc}}

Transistors
Fig

There are transistors that are referred to as switching transistors due to the speed with which they can switch from one voltage level to the other. In Fig the periods of time defined as tsts, tdtd, trtr, and tftf are provided versus collector current. Their impact on the speed of response of the collector output is defined by the collector current response. The total time required for the transistor to switch from the “off” to the “on” state is designated as ton and is defined by

ton=tr+tdton = tr + td

with tdtd the delay time between the changing state of the input and the beginning of a response at the output. The time element trtr is the rise time from 10% to 90% of the final value.

The total time required for a transistor to switch from the “on” to the “off” state is referred to as tofftoff and is defined by

toff=ts+tftoff = ts + tf

where tsts is the storage time and tftf the fall time from 90% to 10% of the initial value.

Logic gates

Transistors
Fig
Transistors
Fig

Bias Stability

The stability of a system is a measure of the sensitivity of a network to variations in its parameters. In any amplifier employing a transistor the collector current ICI_{C} is sensitive to each of the following parameters:

Transistors
Fig

Stability Factors S(ICO)S(I_{CO}), S(VBE)S (V_{BE}), and S(β)S(\beta)

A stability factor SS is defined for each of the parameters affecting bias stability as follows:

S(ICO)=δICδICOS(ICO) = \frac{\delta I_{C}}{\delta I_{CO}}

S(VBE)=δICδVBES(VBE) = \frac{\delta I_{C}}{\delta V_{BE}}

S(β)=δICδβS(\beta) = \frac{\delta I_{C}}{\delta \beta}

AC Analysis - BJT
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig
Transistors
Fig